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1. Introduction 7 Atomic Layer Deposition of High-k Oxides on Graphene Harry Alles, Jaan Aarik, Jekaterina Kozlova, Ahti Niilisk, Raul Rammula and Väino Sammelselg University of Tartu Estonia Graphene that is a single hexagonal layer of carbon atoms with very high intrinsic charge carrier mobility (more than 200 000 cm2/Vs at 4.2 K for suspended samples; Bolotin, et al., 2008) attracts attention as a promising material for future nanoelectronics. During last few years, significant advancement has been made in preparation of large-area graphene. The lateral sizes of substrates for graphene layers have been increased up to 3⁄4 m (Bae et al., 2010) and continuous roll-to-roll deposition of graphene has been published (Hesjedal, 2011). This kind of progress might allow one to apply similar planar technologies for fabricating graphene-based devices in future as currently used for processing of silicon- based structures. After very first experiments (Novoselov et al., 2004), in which the electrical properties of isolated graphene sheets were characterized, a lot of attention has been paid to the similar studies, i.e. investigation of uncovered graphene flakes deposited on oxidized silicon wafers that served as back gates. However, in order to realize graphene-based devices, a high- quality dielectric on top of graphene is required for electrostatic gates as well as for tunnel barriers for spin injection. For efficient control of charge carrier movement dielectric layers deposited on graphene should be very thin, a few nanometers thick, and of very uniform thickness without any pinholes. At the same time, the dielectric should possess high dielectric constant, high breakdown voltage and low leakage current even at a small thickness. And, of course, it is expected that the high mobility of charge carriers in graphene should not be markedly affected by the dielectric layer. In order to make top-gated graphene-based Field Effect Transistor (FET), Lemme et al. (2007) applied evaporation techniques for preparation of a gate stack with ~20 nm thick SiO2 dielectric layer on graphene. They used p-type Si(100) wafers with a boron doping concentration of 1015 cm-3, which were oxydized to a SiO2 thickness of 300 nm. On these wafers, micromechanically exfoliated graphene flakes were sticked. The Ti/Au source and drain electrodes were prepared using optical lift-off lithography. Next, electron beam lift-off lithography was applied to define a top gate electrode on top of the graphene flake covered with the dielectric (Fig. 1a). Lemme et al. were first to demonstrate that the combined effect of back and top gates can be applied to graphene devices. However, measurements of the back-gate characteristics beforePDF Image | GRAPHENE SYNTHESIS CHARACTERIZATION PROPERTIES
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